First Advisor

Robert Paxton

Date of Award

Spring 6-13-2026

Document Type

Thesis

Degree Name

Bachelor of Science (B.S.) in Mechanical Engineering and University Honors

Department

Mechanical and Materials Engineering

Language

English

Subjects

Maskless photolithography, LCD projection lithography, Programmable reticle, Low-cost semiconductor fabrication, Thermal evaporation deposition, Rapid prototyping nanofabrication

Abstract

The semiconductor industry’s continued growth, driven in large part by demand for artificial intelligence hardware, has highlighted the need for greater workforce development in regions adjacent to major fabrication centers like Oregon’s Silicon Forest. This capstone project lays the groundwork for a small scale and student led semiconductor fabrication lab at Portland State University by demonstrating two of the core steps in chip manufacturing: photolithography and thin film deposition. Rather than relying on conventional fixed reticles, this work explores a unique, low cost approach to patterning that uses an ultraviolet-compatible liquid crystal display (LCD) as a programmable reticle, allowing arbitrary patterns to be projected directly onto a photoresist-coated wafer without the need for machined masks. SPR220 positive photoresist was applied to silicon wafer shards via a custom spin coater, exposed through the LCD reticle using a filtered mercury vapor lamp, and developed in a sodium hydroxide solution. Two optical column configurations were built and tested, along with two deposition methods: plasma sputter coating and thermal evaporation of aluminum in a high vacuum diffusion pumped chamber. Direct exposure through the LCD without any reduction optics produced clean, repeatable patterns down to a measured resolution of approximately 33 microns, while the magnification based optical column faced issues within the time and budget available. Thermal evaporation produced usable aluminum films, whereas sputter coating proved unreliable due to insufficient chamber vacuum. These results establish a working baseline platform, in tandem with a documented set of pitfalls, that future PSU capstone teams can build upon to push toward sub-micron features and a more complete in-situ fabrication workflow.

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