An Effective and Application-Specific Evaluation of Low-K Dielectric Integration Integrity Using Copper Pillar Shear Testing

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2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

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Mechanical integrity of low-k dielectrics continues to be an important focus for advanced semiconductor devices. In wafer fabs, while great efforts are made to control individual processing steps, in some cases the overall mechanical quality of the finished silicon dies is not effectively monitored. As a result, defects such as cohesive fracture or interfacial delamination may only manifest themselves during component backend assembly, system board manufacturing and/or field deployment, bringing significant potential disruption and impact to production, product quality, and delivery fulfillment. As silicon and package sizes continue to grow, chip-packaging interaction becomes more significant and the effects of low-k defects also grow as a result. Therefore, it would be of great value to have a quantitative understanding of low-k integrity quality as early as possible, ideally at the wafer or bare die level. The adoption of Cu pillars on fine-pitch flip chips has provided an opportunity for such a purpose. Mechanical tests such as shear testing on individual Cu pillars can be performed, and the response data can be an indicator of the integration quality of the low-k stack. In this study we present results of Cu pillar shear testing on both known-bad and known-good wafer lots of the same device. Response data including load-distance curves and ultimate fracture strength are analyzed and presented. In addition, finite element models have been developed to simulate the test structure and shear testing process. Effects of multiple contributing factors to the shear testing response are evaluated and the results are compared with real shear testing results.


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