Sponsor
Portland State University. Department of Electrical and Computer Engineering
Term of Graduation
2011
Date of Publication
2011
Document Type
Dissertation
Degree Name
Doctor of Philosophy (Ph.D.) in Electrical and Computer Engineering
Department
Electrical and Computer Engineering
Language
English
Subjects
Three-dimensional integrated circuits -- Design and construction, Integrated circuits -- Very large scale integration -- Computer-aided design, Semiconductor industry -- Technological innovations
DOI
10.15760/etd.2804
Physical Description
1 online resource (xii, 221 pages)
Abstract
We have developed a placement-aware 3-D floorplanning algorithm that enables additional wirelength reduction by planning for 3-D placement of logic gates in selected circuit modules during the floorplanning stage. Thus it also bridges the existing gap between 3-D floorplanning and 3-D placement. To reduce the solution space of 3-D floorplanning which is known to be an NP-hard problem, we derive a set of feasibility conditions on the topological representation of a floorplan. In addition, we have designed a fast module packing algorithm that satisfies a set of constraints for placement-aware 3-D floorplanning. Furthermore, we have designed an efficient evolutionary algorithm that is used in the proposed 3-D floorplanning algorithm for multi-objective combinatorial optimization. Our results show that the proposed placement-aware 3-D floorplanning algorithm is very fast, and it reduces the system level total wirelength by 9.8% compared to existing state-of-the-art floorplanning tools that do not plan for 3-D placement of floorplanning modules.
Rights
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Persistent Identifier
https://archives.pdx.edu/ds/psu/17116
Recommended Citation
Nain, Rajeev Kumar, "Floorplan Design and Yield Enhancement of 3-D Integrated Circuits" (2011). Dissertations and Theses. Paper 2810.
https://doi.org/10.15760/etd.2804
Comments
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