First Advisor

Marek Perkowski

Date of Publication

1988

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical Engineering

Department

Electrical Engineering

Language

English

Subjects

Parallel processing (Electronic computers), Computer architecture, Matrices -- Data processing, Algorithms

DOI

10.15760/etd.5680

Physical Description

1 online resource (269 p.)

Abstract

In this thesis, we propose a new systolic architecture which is based on the Faddeev's algorithm. Because Faddeev's algorithm is inherently general purpose, our architecture is able to perform a wide class of matrix computations. And since the architecture is systolic based, it brings massive parallelism to all of its computations. As a result, many matrix operations including addition, multiplication, inversion, LU-decomposition, transpose, and solutions to linear systems of equations can now be performed extremely fast. In addition, our design introduces several concepts which are new to systolic architectures:

- It can be re-configured during run time to perform different functions with the uses of various control signals propagating throughout the arrays.

- It allows for maximum overlaps of processing between consecutive computations, thereby increasing system throughput.

Rights

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Comments

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Persistent Identifier

http://archives.pdx.edu/ds/psu/21241

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