Sponsor
Portland State University. Department of Electrical Engineering
First Advisor
W. Robert Daasch
Date of Publication
1988
Document Type
Thesis
Degree Name
Master of Science (M.S.) in Electrical and Computer Engineering
Department
Electrical Engineering
Language
English
Subjects
Electric resistance -- Mathematical models, Metal oxide semiconductors -- Mathematical models
DOI
10.15760/etd.5686
Physical Description
1 online resource (91 p.)
Abstract
The voltage controlled resistance model is developed for a reliable MOS transistor resistance mapping. The model includes both system and local parameters, and incorporates the effect of rise and fall time variations on the gate delay. MOS transistor resistance mapping is applied in logic simulation and timing verification. Also, it can be used in automatic transistor sizing and critical path analysis.
Rights
In Copyright. URI: http://rightsstatements.org/vocab/InC/1.0/ This Item is protected by copyright and/or related rights. You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).
Persistent Identifier
http://archives.pdx.edu/ds/psu/21270
Recommended Citation
Jia, Joey Zong-yi, "Voltage controlled resistance model for MOS transistors" (1988). Dissertations and Theses. Paper 3802.
https://doi.org/10.15760/etd.5686
Comments
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