Sponsor
Portland State University. Department of Physics
First Advisor
Raj Solanki
Date of Publication
Spring 5-21-2018
Document Type
Dissertation
Degree Name
Doctor of Philosophy (Ph.D.) in Applied Physics
Department
Physics
Language
English
Subjects
Integrated circuits -- Testing, Signal processing, Soft errors (Computer science)
DOI
10.15760/etd.6259
Physical Description
1 online resource (vii, 96 pages)
Abstract
For reliable digital communication between devices, the sources that contribute to data sampling errors must be properly modeled and understood. Clock jitter is one such error source occurring during data transfer between integrated circuits. Clock jitter is a noise source in a communication link similar to electrical noise, but is a time domain noise variable affecting many different parts of the sampling process. Presented in this dissertation, the clock jitter effect on sampling is modeled for communication systems with the degree of accuracy needed for modern high speed data communication. The models developed and presented here have been used to develop the clocking specifications and silicon budgets for industry standards such as PCI Express, USB3.0, GDDR5 Memory, and HBM Memory interfaces.
Rights
In Copyright. URI: http://rightsstatements.org/vocab/InC/1.0/ This Item is protected by copyright and/or related rights. You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).
Persistent Identifier
https://archives.pdx.edu/ds/psu/25571
Recommended Citation
Martwick, Andrew Wayne, "Clock Jitter in Communication Systems" (2018). Dissertations and Theses. Paper 4375.
https://doi.org/10.15760/etd.6259