Portland State University. Department of Physics
Date of Award
Doctor of Philosophy (Ph.D.) in Applied Physics
1 online resource (vii, 96 pages)
For reliable digital communication between devices, the sources that contribute to data sampling errors must be properly modeled and understood. Clock jitter is one such error source occurring during data transfer between integrated circuits. Clock jitter is a noise source in a communication link similar to electrical noise, but is a time domain noise variable affecting many different parts of the sampling process. Presented in this dissertation, the clock jitter effect on sampling is modeled for communication systems with the degree of accuracy needed for modern high speed data communication. The models developed and presented here have been used to develop the clocking specifications and silicon budgets for industry standards such as PCI Express, USB3.0, GDDR5 Memory, and HBM Memory interfaces.
Martwick, Andrew Wayne, "Clock Jitter in Communication Systems" (2018). Dissertations and Theses. Paper 4375.
Available for download on Tuesday, May 21, 2019