Sponsor
Portland State University. Department of Electrical Engineering
First Advisor
Marek A. Perkowski
Term of Graduation
Fall 1994
Date of Publication
10-27-1994
Document Type
Thesis
Degree Name
Master of Science (M.S.) in Electrical and Computer Engineering
Department
Electrical Engineering
Language
English
Subjects
Electronic digital computers -- Circuits -- Design, VHDL (Computer hardware description language), ADL (Computer hardware description language), Computer algorithms, DIADES (Computer program)
DOI
10.15760/etd.6660
Physical Description
1 online resource (134 pages)
Abstract
This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADES, a design automation system developed at PSU, starts the synthesis process from a language called ADL. The major part of this thesis deals with transforming the ADL -based DIADES system into a VHDL -based DIADES system. In this thesis I have upgraded and modified the existing DIADES system so that it becomes a preprocessor to a comprehensive VHDL -based design system from Mentor Graphics.
The high-level synthesis in the DIADES system includes two stages: data path synthesis and control unit synthesis. The conversion of data path synthesis is done in this thesis. In the DIADES system a digital system is described on the behavioral level in terms of variables and operations using the language ADL. The digital system described in ADL is compiled to a format called GRAPH language. In the GRAPH language the behavior of a digital system is represented by a specific sequence of program statements. The descriptions in the GRAPH language is compiled to a format called STRUCT language. The system is described in the STRUCT language in terms of lists of nodes and arrows. The main task of this thesis is to convert the descriptions in the GRAPH language and the descriptions in the STRUCT language to the VHDL format. All the generated VHDL Code will be Mentor Graphics VHDL format compatible, and all the VHDL code can be compiled, simulated and synthesised by the Mentor Graphics tools.
Rights
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Persistent Identifier
https://archives.pdx.edu/ds/psu/27916
Recommended Citation
Palanisamy, Karthikeyan, "High Level Preprocessor of a VHDL-based Design System" (1994). Dissertations and Theses. Paper 4776.
https://doi.org/10.15760/etd.6660
Comments
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