First Advisor

W. Robert Daasch

Term of Graduation

Summer 1997

Date of Publication

7-1-1997

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Language

English

Subjects

Integrated circuits -- Large scale integration -- Noise, Complementary metal oxide semiconductors

DOI

10.15760/etd.7186

Physical Description

1 online resource (2, vii, 69 pages)

Abstract

In recent years, strong demand for high-performance electronic products has fueled the need for high-speed and high-integration VLSI circuits. This demand is expected to continue growing in the future, which will lead to development of IC's that are much more compact and operate at higher frequencies. As a result, preserving signal integrity for proper IC communications becomes an increasingly difficult challenge.

In this thesis, an understanding of IC noise in relation to IC packaging is sought. An IC package is modeled with sophisticated 3-D simulators to extract its corresponding parasitics. These parasitics, expressed in terms of resistance, inductance, and capacitance (RLC), are lumped into their RLC circuit equivalent, and are incorporated into I/O circuits to form a simulatable IC noise model. In addition to SPICE analyses, the behavior of noise is modeled mathematically, and the results are compared to measurement.

With sufficient understanding of IC noise behavior, two circuits are proposed to effectively control IC noise. The first circuit is a modified I/O circuit that monitors the local output switching condition, and intelligently adjusts its slew rate such that the I/O can switch as fast as possible without jeopardizing noise performance. The second circuit is a PVT-compensation control circuit, which senses process (P), voltage (V), and temperature (T) variations, and compensates the I/O circuit's current drive accordingly. This feature makes the I/O circuits more robust under a range of environmental stress.

From analyses and simulations, the proposed I/O and PVT-compensation control circuits show great potential for IC noise control. They control IC noise to less than 10% variation between single and multiple simultaneous output switchings as compared to a conventional I/O circuit with 56% variation. The proposed circuits also show potential for reduced power dissipation in the I/O circuits by a factor of 3. Finally, applications of these circuits are discussed with respect to test and program time reduction as well as commonly used asynchronous circuit interface.

Rights

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Comments

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Persistent Identifier

https://archives.pdx.edu/ds/psu/30593

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