Sponsor
Portland State University. Department of Electrical Engineering.
First Advisor
W. Robert Daasch
Term of Graduation
Winter 1997
Date of Publication
3-1997
Document Type
Thesis
Degree Name
Master of Science (M.S.) in Electrical and Computer Engineering
Department
Electrical Engineering
Language
English
Subjects
Integrated circuits -- Very large scale integration, Continuous-time filters, Complementary metal oxide semiconductors
DOI
10.15760/etd.7617
Physical Description
1 online resource (xii, 83 pages)
Abstract
Automatic synthesis of digital VLSI layout has been available for many years. It has become a necessary part of the design industry as the window of time from conception to production shrinks with ever increasing competition. However, automatic synthesis of analog VLSI layout remains rare.
With digital circuits, there is often room for signal drift. In a digital circuit, a signal can drift within a range before hitting the threshold which triggers a change in logic state. The effect of parasitic capacitances for the most part, hinders the timing margins of the signal, but not its functionality. The logic functionality is protected by the inherent noise immunity of digital circuits.
With analog circuits, however, there is little room for signal drift. Parasitic directly influence signal integrity and the functionality of the circuit. The underlying problem, that the automatic VLSI layout programs face, is how to minimize this influence.
This thesis describes a software tool that was written to show that the minimization of parasitic influence is possible in the case of automatic layout of continuous-time filters using transconductance-capacitor methods.
Rights
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Persistent Identifier
https://archives.pdx.edu/ds/psu/36240
Recommended Citation
Han, Wei, "Automatic Synthesis of VLSI Layout for CMOS Continuous-Time Filters" (1997). Dissertations and Theses. Paper 5746.
https://doi.org/10.15760/etd.7617