Sponsor
Portland State University. Department of Speech Communication
First Advisor
Marek Perkowski
Term of Graduation
Spring 1998
Date of Publication
1998
Document Type
Thesis
Degree Name
Master of Science (M.S.) in Electrical and Computer Engineering
Department
Electrical and Computer Engineering
Language
English
Subjects
Computer architecture, Algebra, Boolean -- Data processing, Field programmable gate arrays
DOI
10.15760/etd.8172
Physical Description
1 online resource (vi, 206 pages)
Abstract
Presented in this thesis are new approaches to column compatibility checking and column-based input/output encoding for Curtis decompositions of switching functions. These approaches can be used in Curtis-type functional decomposition programs for applications in several scientific disciplines. Examples of applications are: minimization of combinational and sequential logic) mapping of logic functions to programmable logic devices such as CPLDs, MPGAs, and FPGAs, data encryption, data compression, pattern recognition) and image refinement. Presently, Curtis-type functional decomposition programs are used primarily for experimental purposes due to performance, quality, and compatibility issues. However) in the past few years a renewal of interest in the area of functional decomposition has resulted in significant improvements in performance and quality of multi-level decomposition programs.
The goal of this thesis is to introduce algorithms that can significantly improve the performance and quality of Curtis-type decomposition programs. In doing so, it is hoped that a Curtis-type decomposition program, complete with efficient, high quality algorithms for decomposition, will be a feasible tool for use in one or more practical applications.
Various testing and analyses were performed in order to evaluate the potential of algorithms presented in this thesis for use in a high quality Curtis-type decomposition program. Testing was done using a binary input, binary output Curtis-type decomposition program MULTIS/GUD. This program was implemented here at Portland State University by the Portland Oregon Logic Optimization Group.
Rights
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Persistent Identifier
https://archives.pdx.edu/ds/psu/39705
Recommended Citation
Chen, Qihong, "The Design of Cube Calculus Machine Using Sram-Based Fpga Reconfigurable Hardware Dec’s Perle-1 Board" (1998). Dissertations and Theses. Paper 6319.
https://doi.org/10.15760/etd.8172
Comments
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