Sponsor
Portland State University. Department of Electrical and Computer Engineering
First Advisor
Malgorzata E. Chrzanowska-Jeske
Term of Graduation
Winter 2000
Date of Publication
2000
Document Type
Thesis
Degree Name
Master of Science (M.S.) in Electrical and Computer Engineering
Department
Electrical and Computer Engineering
Language
English
Subjects
Computer algorithms, Algorithms, Integrated circuits -- Very large scale integration -- Computer-aided design, Microcomputers -- Buses, Microprocessors -- Design and construction
Physical Description
1 online resource (iv, 88 pages)
Abstract
In this thesis, we propose a novel algorithm for the interconnect driven floorplanning problem that integrates bus planning with floorplanning. This integrated floorplanner is intended for bus-based designs in which the layout is considered to be a set of blocks connected through buses. Each bus consists of a large number of wires. Our floorplanner allocates the exact location and shape of the interconnect (both above and between the circuit blocks) and ensures routability as well as optimizes the timing goals. Our experiments with benchmarks clearly show the superiority of integrated floorplanning approach over the classical floorplan-analyze-and-then-refloorplan approach. Our initial results show that our floorplans, which are routable and meet all timing constraints, are 12-13% better in area as compared to traditional floorplanning algorithms.
Rights
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Persistent Identifier
https://archives.pdx.edu/ds/psu/42582
Recommended Citation
Rafiq, Faran, "Integrated Floorplanning and Buffer Insertion for Bus-Based Microprocessor Designs" (2000). Dissertations and Theses. Paper 6710.