First Advisor

David C. Burnett

Term of Graduation

Summer 2025

Date of Publication

8-27-2025

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Language

English

Subjects

Phase Noise, Voltage Controlled Oscillators

Physical Description

1 online resource (xi, 78 pages)

Abstract

This thesis presents techniques for enhancing the frequency stability of ring oscillators (ROs) for crystal-free wireless communication systems. The first major contribution is a tutorial-style study of frequency stability metrics, providing clear definitions, conversions methods, and comparative analysis of commonly used figures of merit such as phase noise, Allan deviation, and jitter. The second contribution addresses the challenges of simulating phase noise in free-running ROs. Key techniques including Periodic Steady-State Noise (PNoise), Harmonic Balance Noise (HBNoise), and transient noise analysis are evaluated in terms of accuracy, convergence behavior, and simulation runtime. Based on these results, practical guidelines are offered for effective simulation of oscillator phase noise. This work lays the groundwork for the design efforts pursued in this thesis and the author's ongoing Ph.D. research.

The core design contribution is a Digitally Controlled Ring Oscillator (DCRO) that employs current-starved inverter delay cells with binary-weighted transistor DACs. These DACs enable real-time adjustment of effective transistor widths via digital control words, allowing dynamic symmetry tuning of individual delay stages to mitigate flicker noise upconversion without requiring a large number of analog I/Os. A prototype oscillator, as well as an RF front-end for its testing, has been submitted for fabrication in Intel's 16 nm FinFET process, with silicon return expected in Q4 2025. Looking ahead, two system-level control strategies are proposed to maintain both short-term phase noise performance and long-term frequency stability without a crystal reference. The first uses a charge-pump-based feedback loop driven by the received RF signal but is limited by poor channel selectivity. The second is a dual-mode architecture comprising: (1) a calibration mode using an external PLL to sweep across temperature and voltage corners, generating a multi-dimensional lookup table (LUT) of control words, and (2) a free-running mode where the PLL is disabled, and the DCRO is stabilized using on-chip LUT-based control. Together, the proposed DCRO architecture and control strategies aim to enable a digitally tunable, low-power, inductor-free solution for next-generation crystal-free wireless communication systems.

Rights

©2025 Haziq Rohail

In Copyright. URI: http://rightsstatements.org/vocab/InC/1.0/ This Item is protected by copyright and/or related rights. You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).

Persistent Identifier

https://archives.pdx.edu/ds/psu/44158

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