Implementation and Performance of Error Correction Codes for High-Speed Computer Networks

Author

• Jochen Spengler, Portland State University

Sponsor

Portland State University. Department of Electrical and Computer Engineering

First Advisor

Douglas V. Hall

Term of Graduation

Summer 1999

Date of Publication

9-7-1999

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Language

English

Subjects

Error-correcting codes (Information theory), Computer networks

Physical Description

1 online resource (2, ix, 103 pages)

Abstract

During the transmission of data there is always a possibility that errors occur and some pieces are modified. If the receiver detects an error it either sends a request for retransmission or, like in networks using Ethernet, it does not send an acknowledgment for the erroneous frame. In this case the sender waits a certain time and retransmits the frame. With the development of faster computer networking hardware and the need for more real-time applications, these errors have become a major concern. Long retransmission latencies and the need for large memories for buffering drive the development of more reliable network components. One way to improve the error performance of computer networks is to build better transceivers and cables. Another way is to encode the data and add redundant information to make it possible to detect and correct errors at the receiver side.

The three most widely used error correction codes, Reed-Solomon, convolutional and Turbo codes, are described in this thesis. Because of their superior error performance Reed-Solomon codes are studied in more detail. Standard Reed-Solomon decoding uses complex algorithms, so currently available hardware implementing these algorithms only reaches into the Megabit/s range. To achieve the high coding speeds needed for modern computer networks several tradeoffs have to be made. Based on our research, the best balance of these tradeoffs is the (255,253) Reed-Solomon code. This code was implemented and optimized for Gigabit Ethernet transmission speeds. A novel decoding scheme using a ROM lookup table is presented to avoid the gate complexity and slow speed of standard decoders. All devices were implemented in VHDL and simulated with ModelTechnology's ModelSim_TM. For the timing analysis, the ALTERA^® MAX+PLus^® I I tool and FLEX^® l0K FPGA and MAX^® 7K high-speed PLD devices were used.

The simulations show an error performance improvement of 2 to 6 orders of magnitude assuming an initial channel bit error rate of 10^-8 to 10^-12. Encoder and decoder are working with a throughput of 1 Gigabit/s. Their gate complexity is very low and several could be implemented inside a single logic device to provide a scalable version for higher speeds and better error performance.

Rights

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Persistent Identifier

https://archives.pdx.edu/ds/psu/44647

Recommended Citation

Spengler, Jochen, "Implementation and Performance of Error Correction Codes for High-Speed Computer Networks" (1999). Dissertations and Theses. Paper 7043.