Systems Science Friday Noon Seminar Series

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Date

5-13-2011

Abstract

In this presentation I will describe the latest version of the Numenta HTM Cortical Learning Algorithm and why it is interesting for doing research into radical new computer architectures. Then I will discuss the hardware acceleration research we are doing, and briefly look at some preliminary applications development.

Biographical Information

Dan Hammerstrom received the BS degree from Montana State University, the MS degree from Stanford University, and the PhD degree from the University of Illinois. He was an Assistant Professor in the Electrical Engineering Department at Cornell University from 1977 to 1980. In 1980 he joined Intel in Oregon, where he participated in the development and implementation of the iAPX-432, the i960, and iWarp. In 1988 he founded Adaptive Solutions, Inc., which specialized in high performance silicon technology (the CNAPS chip set) for image processing and pattern recognition. He is now a Professor in the Electrical and Computer Engineering Department and Associate Dean for Research in the Maseeh College of Engineering and Computer Science at Portland State University. Prof. Hammerstrom has joint appointments in the IDE (Information, Computation, and Electronics) Department at Halmstad University, Halmstad, Sweden and in the Biomedical Engineering Department of the Oregon Health & Science University.

Subjects

Computer architecture -- Design, Computer algorithms, Machine learning, Computational intelligence, Signal processing -- Digital techniques

Disciplines

Systems Architecture | Theory and Algorithms

Persistent Identifier

https://archives.pdx.edu/ds/psu/31201

Rights

© Copyright the author(s)

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Hardware Acceleration of Inference Computing: The Numenta HTM Algorithm

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